1. Field of the Invention
The invention presents a method of varying the timing of an integrated circuit design by adjusting the voltage supplies to accommodate revised timing requirements.
2. Description of the Related Art
To remain competitive in today's ASIC environment, design centers are becoming increasingly sensitive to Turn Around Time (TAT) that measures the time it takes to go from design concept to production hardware. A decrease in TAT correlates to an increase in design center through-put which typically translates directly to higher revenues. In addition to higher revenues, a reduction in TAT also leads to increased customer satisfaction and business opportunities. Studies have shown that difficulties in static timing closure is often a major contributor to excessive TAT.
These difficulties are often the result of using timing models that reflect only the extreme process corners or variations in the manufacturing line. Process extremes are defined by both front end process variations that affect gate delay and back end process variations that affect wire delay. For timing closure, all timing requirements for the design must today be met at both the slow and fast process extremes represented by the timing models. The farther apart these process extremes become, the more difficult and resource consuming it is to meet static timing requirements.
The ability to accurately reduce these process extremes from a timing model's perspective would greatly facilitate many situations that do not require timing closure at the process extremes. One example of this is timing closure for prototype hardware. In this situation, product yield would be sacrificed for the ability to get prototype hardware to the customer much sooner than would be possible if doing timing closure at the process extremes. Another example is customers that are willing to pay a premium to offset product yield loss on production hardware in order to reduce TAT or design for higher performance hardware. A third example is when the manufacturing line deliberately shifts or changes the process extremes as the result of line tailoring.
Each of these examples would require the timing models to adjust to new process corners, however today that translates to a complete re-characterization of the models, a task that would take months and many resources. This disclosure proposes a new methodology that allows existing fixed process timing models to dynamically adjust to user specified process extremes for both front end and back end variations without the need to re-characterize the models.